A TFT-LCD (thin film transistor liquid crystal display) is a principal flat-panel display device. An existing array substrate includes gate lines, data lines, TFTs (thin film transistors) and pixel electrodes. The gate lines are arranged on a base substrate horizontally, the data lines are arranged on the base substrate longitudinally, and the TFTs, as active switch elements, are arranged at junctions between the gate lines and the data lines.
As shown in FIG. 1, the existing array substrate includes a gate electrode 10, a gate insulating layer 20, an active layer 30, a source electrode 50, a drain electrode 60, and a passivation layer 70, which are all arranged on a base substrate 80. The gate electrode 10 is formed with the gate lines integrally, the source electrode 60 and the drain electrode 60 are formed with the data lines integrally, and the drain electrode 60 is electrically connected to a pixel electrode 90. When an ON signal is inputted to the gate line, the active layer 30 will be electrically conductive, and a data signal from the data line will be transmitted from the source electrode 50 to the drain electrode 60 via a TFT channel 31, and finally to the pixel electrode 90. Upon the receipt of the signal, the pixel electrode 90 will form, together with a common electrode 91, an electric field for driving liquid crystals to rotate. Currently, in order to be adapted to a higher level of integration, a high PPI (pixels per inch) product has become a mainstream of the display device. However, more requirements shall be met when preparing the high PPI product, and seven patterning processes are desired to form structural patterns, so as to achieve the integration of GOA (Gate Driver on Array, which refers to a technique where gate driver ICs are directly manufactured on the array substrate so as to replace driver ICs made by external silicon wafers). Due to the application of the GOA technique, it is able to form the gate driver ICs at a periphery of a panel, so as to reduce the process steps, reduce the production cost, and enhance an integration level of the TFT-LCD panel, thereby to thin the panel and provide sufficiently small via-holes. Each patterning process includes such processes as exposing with a mask, developing, etching and removing, and the etching process includes both dry etching and wet etching. Hence, the number of patterning processes may be used to measure whether or not a method for manufacturing the TFT-LCD array substrate is complex, and a decrease in the number of patterning processes means a reduction in the production cost.
FIG. 3 shows the procedure for manufacturing the array substrate of a traditional TFT-LCD with an ADS mode. ADSDS (ADvanced Super Dimension Switch, ADS for short) is a wide viewing angle core technique for a planar electrical field system, and its features may be described as forming a multi-dimensional electric field by means of electrical fields generated at edges of slit electrodes within an identical plane and an electrical field generated between a slit electrode layer and a plate electrode layer, so as to enable all the liquid crystal molecules between the slit electrodes and right above the electrodes within a liquid crystal cell to rotate, thereby to improve the operational efficiency of the liquid crystal molecules and enhance the light transmission efficiency. ADS may be used to improve the image quality of a TFT-LCD product, and has such advantages as high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration and free of push Mura. At first, the gate lines are formed on a glass substrate by a first patterning process, and the gate insulating layer 20 and the active layer 30 are deposited, and a pattern of the active layer 30 is formed by a second patterning process. Next, the pixel electrode is deposited, and a pattern of the pixel electrode is formed by a third patterning process. A via-hole (GI via-hole) is formed in the gate insulating layer 20 by a fourth patterning process. A metal layer is then deposited, and patterns of a signal line and the active layer 30 are formed by a fifth patterning process. The signal line is connected to the gate line through the GI via-hole, and the patterns of the signal line and the active layer 30 are formed at a channel region. Then, the passivation layer (PVX) is deposited, and a passivation layer via-hole is formed by a sixth patterning process. Finally, a conductive layer is deposited, and the common electrode is formed by a seventh patterning process. Through the above seven masking processes, the structural patterns of the array substrate will be obtained.
As can be seen from the above, as to the existing method for manufacturing the TFT-LCD array substrate, when manufacturing the high PPI product including the GOA, seven masking processes are usually adopted due to such factors as high wiring density, thus it is unable to increase the yield. Moreover, as to the existing TFT LCD array substrate, the channels are formed by etching, and imperfect channels will be caused due to processes and devices used for the etching. These imperfect channels will occur frequently during the production, and the product quality will be adversely affected.